1. Field of the Invention
The present invention relates to a method for the manufacture of a semiconductor device, and more particularly to improvement in or relating to a method for the manufacture of a semiconductor device of the type having a BOMIS (Buried Oxide MIS) field effect transistor.
2. Description of the Prior Art
A known BOMIS field effect transistor has such a structure as shown in FIG. 1.
In FIG. 1, reference numeral 1 indicates a p type low resistance silicon semiconductor substrate having a resistivity .rho..sub.b of, for example, 1 to 2 .OMEGA..multidot.cm; 2 designates a silicon dioxide (SiO.sub.2) film; 3S identifies a single crystalline silicon semiconductor layer; 3P denotes a polycrystalline silicon semiconductor layer; 4 represents another silicon dioxide film; 5 shows a gate oxide film; 6 refers to a silicon gate electrode; 7 indicates a source region; 8 designates a drain region; 9 identifies a phosphosilicate glass film; 7a denotes a source electrode; and 8a represents a drain electrode.
Such a semiconductor device is manufactured by such a method as described below.
The manufacture starts with the formation of a silicon dioxide film 2 to a thickness of about 1 .mu.m on a p type low resistance (for example, resistivity .rho..sub.b .apprxeq.1 to 2 .OMEGA..multidot.cm) silicon semiconductor substrate 1 through the use of the thermal oxidation method.
The silicon dioxide film 2 is subjected to patterning by ordinary photolithography to form therein a window, through which is exposed a portion of the surface of the single crystal silicon substrate 1.
Then, a silicon semiconductor layer is formed by the epitaxial growth method to cover the silicon dioxide layer 2 and the exposed substrate surface. In this case, the silicon semiconductor layer is composed of a single crystalline silicon semiconductor layer 3S formed on the exposed surface of the single crystal substrate 1 and a polycrystalline silicon semiconductor layer 3P formed on the silicon dioxide film 2. During the growth of the silicon semiconductor layer, an impurity in the substrate 1 is caused to diffuse out therefrom into the single crystalline silicon semiconductor layer 3S to make it p.sup.- type. The silicon semiconductor layers 3S and 3P are respectively formed about 1 .mu.m thick.
Following this, the polycrystalline silicon semiconductor layer 3P is partly oxidized to form a silicon dioxide film 4 of about 1 .mu.m in thickness, by means of selective thermal oxidation using, for example, a silicon nitride (Si.sub.3 N.sub.4) film as a mask. In this case, the portion of the polycrystalline silicon semiconductor layer 3P to be selectively oxidized is usually etched shallow, prior to the thermal oxidation, so that the surfaces of the silicon dioxide film 4 to be formed and the polycrystalline silicon semiconductor layer 3P may be substantially flush with each other.
After removing the mask of the silicon nitride film, a thin silicon dioxide film is formed by thermal oxidation to extend on the silicon semiconductor layers 3S and 3P and a polycrystalline silicon layer is formed by chemical vapor deposition on the abovesaid thin silicon dioxide film.
Thereafter, the abovesaid polycrystalline silicon layer and thin silicon dioxide film are subjected to patterning by the ordinary photolithography, forming a gate oxide film 5 and a silicon gate electrode 6.
After this, for example, arsenic ions (As.sup.+) are injected by ion implantation to form an n.sup.+ type source region 7 and an n.sup.+ type drain region 8, while at the same time rendering the silicon gate electrode 6 n.sup.+ type. The sheet resistance .rho.s of each of the portions thus made n.sup.+ type is 10 to 20 .OMEGA./.quadrature..
Next, a phosphosilicate glass film 9 is formed 0.8 .mu.m or more thick by the chemical vapor deposition and then the film 9 is patterned by the ordinary photolithography to provide a windows for contact with the electrodes.
Thereafter, an electrode metal film is formed and then patterned to form a source electrode and wire 7a and a drain electrode and wire 8a, and further, an insulating film (not shown) is formed which serves as a surface protecting film; thus, a device is completed.
The above manufacturing process employs, for imparting the p.sup.- conductivity type to the single crystalline silicon semiconductor layer 3S, the out-diffusion of an impurity from the substrate 1 during the epitaxial growth. This method is desirable from the viewpoint of reducing the number of manufacturing steps involved on the one hand but has demerits on the other hand. Namely, since it is necessary to perform the out diffusion of an impurity simultaneously with the epitaxial growth of the silicon semiconductor layer, the step therefor requires a high temperature and much time. Accordingly, this step greatly affects the manufacturing cost of the device and causes warping of the substrate and a crystal defect.
With the present semiconductor technology, it will be possible to impart a suitable impurity concentration to the single crystalline silicon semiconductor layer 3S by doping it with an impurity during the growth of the aforesaid silicon semiconductor layer; with this method, however, the impurity concentration is difficult to control and, in obtaining a proper impurity concentration, there is a problem in terms of reproducibility. Further it is also possible to dope an impurity by the ion implantation after the growth of the silicon semiconductor layer but, in this case, too, high-temperature and time-consuming annealing is required and such annealing is an obstacle to the fabrication of a device with high integration density.